Many types of semiconductor devices are made using similar manufacturing procedures. A starting substrate, usually a thin wafer of silicon or gallium arsenide, is doped, masked, and etched through several process steps, the steps depending on the type of devices being manufactured. This process yields a number of die on each wafer produced. Each die on the wafer is given a brief test for full functionality, and the nonfunctional die are mechanically marked or mapped in software. This brief test is only a gross measure of functionality, and does not insure that a die is completely functional or has specifications that would warrant its assembly in a package.
If the wafer has a yield of grossly functional die which indicates that a good quantity of die from the wafer are likely to be fully operative, the die are separated with a die saw, and the nonfunctional die are scrapped while the rest are individually encapsulated in plastic packages or mounted in ceramic packages with one die in each package. After the die are packaged they are rigorously electrically tested. Components which turn out to be nonfunctional or which operate at questionable specifications are scrapped or devoted to special uses.
Semiconductor devices, and specifically memory devices such as dynamic random access memories (DRAMs), function by having the ability to store a charge on a storage node. A typical DRAM cell is illustrated as shown in the FIG. 1 cross section. The transistor cell comprises source 10, drain 12, and channel 14 regions implanted into a substrate 16 of semiconductor material. In the cross section of FIG. 1, a portion of the gates 18 are formed over field (thick) oxide 20, and a portion of the gates 18 are separated from the channel 14 by gate (thin) oxide 22. Not shown in the FIG. 1 cross section is that each gate has a portion overlying the field oxide and a portion overlying the gate oxide. The storage node 24 contacts the transistor source 10, and the digit line 26 contacts the transistor drain 12.
To write a "0" to the storage node, for example, the digit line is grounded, the access gate is turned on, and any charge drains from the storage node across the channel to the drain. Conversely, to store a "1" on the storage node, the digit line is brought to +5 V, the access gate is turned on, and a charge flows from the drain to the source across the channel to charge the storage node to +5 V.
To read the cell, the digit line is brought to a reference voltage (for example 2.5 volts) which is monitored by a sense amplifier, and the access gate corresponding to the cell of interest is turned on. If the storage node is storing a low, the voltage on the digit line decreases, which is detected by the sense amplifier. Similarly, if the storage node is storing a high, the voltage on the digit line increases slightly, which is detected by the sense amp. Other methods of reading from and writing to the cell are also possible.
A voltage adjust implant to the channel region determines the potential between the storage node and the digit line which is required to trip the transistor, referred to as the threshold voltage (V.sub.t). A threshold voltage of 2 V, for instance, would require a potential of 2 V between the digit line and the storage node to trip the transistor. If the V.sub.t is too low, the transistor will turn on during normal voltage differences such as voltage spikes. If low enough, the transistor can stay on all the time, which will result in a functional short between the digit line and the storage node. Conversely, if V.sub.t is too high, the transistor will not trip, thereby resulting in a functional open between the storage node and the digit line. During the voltage adjust implant of an N-type enhancement mode device, positive ions such as boron are implanted into the channel region to increase the trip voltage, while negative ions such as arsenic decreases the trip voltage. The opposite is true for P-type and depletion mode devices, in which negative ions increase V.sub.t, while positive ions implanted in the channel region decrease the trip voltage. Note that the invention herein is described in terms of an N-type device, but its use with P-type devices is also possible by one of skill in the art.
One problem which can adversely affect device yields is contamination of the device from mobile ions, referred to as pseudoinjection. Mobile ion contamination, for example by sodium ions, can result from various process steps used during the manufacture of the semiconductor device and occurs when ions enter the substrate or other features thereby changing the conductivity of the feature. The ions are known to be more mobile at elevated temperatures. One type of mobile ion contamination occurs during elevated temperatures as the device is operating, for example during a device reliability test at elevated temperatures (burn-in) or during operation in the enclosed space of a computer housing. This can result in N-channel inversion, which effectively turns an enhancement device into a depletion device.
These positive ions have been found to travel easily through layers of tetraethyl orthosilicate (TEOS) and layers of borophosphosilicate glass, (BPSG) which are commonly used as dielectric layers during the manufacture of semiconductors, and may have the ability to travel through other materials as well. An N-type enhancement device which has contamination of the gate oxide from positive ions will have a lowered V.sub.t because of a biased gate above the channel region, thereby resulting in the problems described above.
Contamination of other dielectric features can result in other problems which are known in the art of semiconductor manufacture. Contamination can result at the periphery of a semiconductor die when a BPSG, TEOS, or other oxide layer is exposed during separation of the die during the wafer saw step, thereby resulting in failed bits or other features around the periphery of the die.
One method of preventing mobile ion contamination during this step is to terminate the oxide features along the saw kerf as shown in FIG. 2. A die incorporating this method of oxide termination comprises the use of passivation layers such as oxide 30 and nitride 32 around the periphery near the saw kerf 34 to prevent mobile ions from entering the BPSG 36 or the TEOS 38. One problem with terminating the oxide in this manner is that it adds a mask step which increases the cost of the process and can be misaligned, thereby requiring an increase in the size of the die to allow for misalignment. In addition, the oxide passivation 30 extends out about 5 microns (.mu.) past the edge of the active area 40, and the nitride extends out about 5.mu. past the oxide 30 thereby increasing the size of each die which is contrary to design goals.
A semiconductor device which has reduced susceptibility to mobile ion contamination which does not require an additional mask step and does not increase the die size would be a desirable structure.